# Verification

This Chapter explains how to use the verification functionality of ILAng to generate verification target to work with existing model checkers. Currently we support Cadence JasperGold, CoSA, Pono (previously named CoSA2). For other Verilog model checker, we can generate a standalone Verilog with embedded assumptions and assertions using the SVA format.

For verification, you will need (1) an ILA model (2) the Verilog module (3) the refinement relation to map ILA and Verilog, this is shown in the following figure.

![](https://2768939566-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FGvPvl0ieQJyhh8vj0Qs6%2Fuploads%2Fgit-blob-d8b0afe6fe96320e87d4ba787dc52d172ced2469%2Frtl-verify-arch.png?alt=media)
